1. Field of the Invention
The present invention relates to a read/write architecture for a magnetoresistive random access memory (MRAM) addressable via word lines and bit lines. The MRAM has a multiplicity of ferromagnetic memory elements that are disposed at crossovers between word lines and bit lines. The memory elements at the crossovers form rows and columns of a matrix, which furthermore each contain two ferromagnetic layers separated by a separating layer, and whose resistance perpendicular to the layer sequence is in each case higher than that of the word lines and of the bit lines and depends on the magnetization state of the ferromagnetic layers.
As is known, MRAMS are non-volatile random access memories which, in comparison with other types of non-volatile and also volatile memories such as, for example, DRAMs, FRAMS (ferroelectric RAMs), EEPROMS (electrically erasable and programmable ROMs or read-only memories) and FLASH memories, are distinguished by advantages such as, in particular, high storage densities ranging into the order of magnitude of 100 Gbits/chip or more, simple process architectures and hence low fabrication costs per bit.
The cell arrays of MRAMS expediently contain metallic word lines and bit lines, also called write lines and read lines, which are disposed in a matrix-like manner and are disposed one above the other such that they respectively run in the x-direction and y-direction in a Cartesian xy coordinate system, and between which the ferromagnetic memory elements are provided at the crossovers between the word lines and the bit lines. The ferromagnetic memory elements contain at least two ferromagnetic layers that lie one above the other and are magnetically decoupled, which is effected by a separating layer provided between the ferromagnetic layers. The separating layer may be a tunneling barrier made, for example, of aluminum oxide (Al2O3) or a non-ferromagnetic conductive layer made, for example, of copper.
The ferromagnetic layers are composed, for example, of iron, cobalt, nickel, permalloy (NiFe), etc., it being possible for them to contain additions such as platinum, for example, which promote a finely crystalline state.
The ferromagnetic layers may have a layer thickness of between 3 and 20 nm, while the separating layer located between them may have a thickness of 1 to 3 nm.
The ferromagnetic layers of each memory element have switching fields of different magnitude and can therefore be subjected to magnetization reversal independently of one another by switching currents in the word lines and bit lines, which form interconnects. In this case, the resistors of the individual memory elements have resistances dependent on the relative magnetization of the ferromagnetic layers that form them. If both ferromagnetic layers are magnetized parallel to one another, then the memory element has a resistance R0, while a resistance R0+xcex94R (xcex94R greater than 0) is present in the case of antiparallel magnetization of the two ferromagnetic layers. The ratio xcex94R/R0 is about 0.1 . . . 0.2. This effect is referred to as the magnetoresistance effect. The term magnetoresistive memory elements is also customary for the ferromagnetic memory elements.
These two resistances of the ferromagnetic layers, that is to say the resistance R0 for parallel magnetization and the resistance R0+xcex94R for the antiparallel magnetization, can be assigned the quantities xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d of binary memories.
Writing to MRAMs is simple, in principle, if the fact that the requisite switching field strengths have to be achieved by the interconnects is disregarded. It has proved more difficult for the information stored as resistances in the memory elements to be read out reliably and as simply as possible, that is to say without the assistance of selection transistors, which enlarge the memory cell areas and make the fabrication process more complex.
Various efforts have already been made to configure the read-out securely and reliably without selection transistors. A principal problem in reading the memory cells disposed in high memory density with a cell area of 4 F2 (F=minimum feature size) is that each memory cell, that is say each resistive element whose resistance is to be determined, is xe2x80x9cshuntedxe2x80x9d through a multiplicity of parallel current paths, which makes it problematic to determine the resistance exactly, especially in large memory cell arrays.
In order to overcome these difficulties, two read-out methods have previously been disclosed for MRAMS.
In the first method, the word lines and the bit lines are electrically insulated from one another, and the read current flows through a relatively small number, for example ten, of memory elements connected in series. The resistance of a relevant memory element can then be inferred from the change in the read current by a relatively complex circuit (in this respect, see the reference by D. D. Tang, P. K. Wang, V. S. Speriosu, S. Le, R. E. Fontana, S. Rishton, IEDM 95-997).
The method requires write currents through the two interconnects (word line and bit line) which cross at the relevant memory element. The number of memory elements connected in series is limited by the relative change in the total resistance, which change becomes ever smaller as the number increases, and the measurement of the current change, which measurement becomes more difficult. The small number of memory elements that can be connected in series with one another necessitates a large outlay on circuitry for the periphery of the memory array and thus results in a large area requirement for the read electronics.
The second read-out method consists in all word lines and bit lines, with the exception of the word line connected to the selected memory cell, being put at xe2x80x9c0xe2x80x9d potential. A potential not equal to zero is applied to the selected word line, while the selected bit line and all other bit lines are brought to a xe2x80x9cvirtualxe2x80x9d zero potential by using an operational amplifier for current measurement (in this respect, see Published, Non-Prosecuted German Patent Application DE 197 40 942 A1).
Both methods have the disadvantage that they are based on the determination of the absolute value of the resistance of the individual memory elements, as a result of which very stringent technological requirements are placed on accurate, reproducible and homogeneous setting of the resistances over the entire memory cell array and also over a semiconductor wafer or a plurality of semiconductor wafers. Equally, it must be taken into consideration here that in the case of the relatively small changes of xcex94R/R0, temperature fluctuations can bring about changes in the resistance which make it more difficult to reliably determine the magnetization states of individual memory elements and hence to read the latter. In addition, in the second method, the finite bit line resistances have the effect that the condition of a virtual zero potential is met only at the ends of the bit lines, with the result that parasitic shunt currents have an adverse effect in the case of long bit lines.
It is accordingly an object of the invention to provide a read/write architecture for a MRAM that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which, in conjunction with a simple construction, allows reliable reading of the memory cell array and does not place unrealistically stringent requirements on the exact, reproducible and homogeneous setting of the resistances of the individual memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, a read/write architecture for a magnetoresistive random access memory (MRAM). The read/write architecture contains bit lines, word lines crossing over the bit lines, and a multiplicity of ferromagnetic memory elements disposed at the crossover points of the word lines and the bit lines and forming rows and columns of a matrix. Each of the ferromagnetic memory elements contains a layered sequence having a separating layer and two ferromagnetic layers separated by the separating layer. The ferromagnetic memory elements have a resistance perpendicular to the layer sequence in each case higher than that of the word lines and of the bit lines and depends on a magnetization state of the ferromagnetic layers. The ferromagnetic memory elements are each connected between one of the word lines and one of the bit lines. At least one of the ferromagnetic memory elements functions as a reference memory element having a known magnetization state. Connections between the reference memory element and each of the ferromagnetic memory elements defines taps of resistance bridges and a resistance ratio of each of the ferromagnetic memory elements to the reference memory element can be determined by the resistance bridges. Each of the resistance bridges includes the reference memory element and one of the ferromagnetic memory elements.
In the case of a read/write architecture according to the invention, the object is achieved by virtue of the fact that the ferromagnetic memory elements are each connected between one of the word lines and one of the bit lines, at least one reference memory element has a known magnetization state, and the resistance ratio of each memory element to the reference memory element can be determined by resistance bridges.
In the case of the read/write architecture according to the invention, then, by use of special external circuitry of the memory cell array, which forms a xe2x80x9cresistor gridxe2x80x9d, the magnetization state of the individual memory elements, that is to say the parallel or antiparallel magnetization of the ferromagnetic layers, is not determined by absolute measurement of the resistancexe2x80x94the customary procedure hitherto in the prior artxe2x80x94but rather by resistance comparison with memory elements of a known magnetization state. In this case, at least one memory element must be provided as a reference memory element, in which case a whole column and/or a whole row of memory elements may expediently also have a known magnetization state. In this case, such a known magnetization state is, for example, a parallel magnetization of both ferromagnetic layers with the low resistance R0 or an antiparallel magnetization of the two resistive layers with the resistance R0+xcex94R (xcex94R greater than 0). The known magnetization state should be written in before the actual read process.
The resistances are compared by resistance bridges, namely half-bridges or full-bridges, which are produced by the abovementioned external circuitry of the resistor grid.
At the center taps of the resistance bridges, voltages arise which make it possible to infer the relative magnitude of the resistances in the resistance bridges and thus the information stored in the individual memory elements, that is to say xe2x80x9c0xe2x80x9d (for example parallel magnetization) or xe2x80x9c1xe2x80x9d (for example antiparallel magnetization).
With vanishing shunt voltage across the resistance bridges, the resistances correspond and both have the value R0, for example. However, if the shunt voltage differs from zero, then the resistance sought has a value that deviates from the resistance of the reference memory element, namely R0+xcex94R, for example.
During reading, by way of example, a voltage xe2x88x92V/2 can be applied to the reference memory element, while the voltage +V/2 can then be applied to a memory element to be read.
The materials for the individual memory elements are the same as has already been mentioned above. The separating layer between the ferromagnetic layers may be composed of, for example Al2O3 (i.e. a barrier layer) or of copper and have a layer thickness of between 1 and 3 nm, while the ferromagnetic layers themselves are constructed in a customary manner from iron, cobalt, nickel, permalloy with corresponding additions (for example platinum) and have a layer thickness of between 3 and 20 nm.
An advantageous development of the invention provides for current followers or amplifiers to be used for resistance comparison purposes in the individual resistance bridges and for their output voltage to be independent of the number m of word lines in the resistor grid. As a result, it is possible to use large cell arrays, so that the area ratio of the memory cell array to the read-out electronic also increases.
An essential advantage of the invention is that it enables a large memory cell array with memory cells without selection transistors, even the measurement signal obtained when reading a memory cell being able to be made independent of the size of the memory cell array with the aid of the abovementioned current follower.
Additional advantages that can be attained by the invention can be summarized as follows. The read-out electronics are constructed comparatively simply and merely have the task of distinguishing between symmetry or asymmetry of the individual resistance bridges. In contrast to the prior art, the measurement signal is completely independent of the absolute value of the individual resistive elements; it merely depends on the voltages applied to the memory cell array and the magnetoresistance effect xcex94R/R0 of the individual memory elements. The technological requirements placed on accuracy, reproducibility and homogeneity in the fabrication of the memory cell array are reduced since reading is based solely on the comparison of resistors that are closely adjacent to one another within the memory cell array. In contrast to the absolute value determination of the resistances which is customary in the case of the prior art, in the case of the read/write architecture according to the invention the measurement signal is used in its full magnitude for distinguishing the two resistance states and is not just contained in a small change in the measurement quantity. Temperature-dictated changes in resistance have no influence on the read signal since they cancel out in the bridge circuit. It is possible to read relatively large memory cell arrays without selection transistors, which results in considerable advantages in respect of storage density, process simplicity and costs per bit. Line resistances of the word lines and of the bit lines are at last partly ineffectual for symmetry reasons.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a read/write architecture for a MRAM, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.